Static Random Access Memory (SRAM) is a commonly used type of memory device that includes one or more memory cells. A typical SRAM cell is made up of six metal-oxide-semiconductor field-effect transistors (MOSFETs). Each memory cell in the SRAM stores information using four of the transistors that form two cross-coupled inverters. This memory cell generally operates in two stable states, denoted as 0 and 1. Two additional access transistors control the access to the memory cell during read and write operations.
Other SRAM cells may use more than four transistors per bit. For example, SRAM used in central processing unit (CPU) caches may use eight transistors, 10 transistors, or more per bit. In some memory devices, SRAM cells may be configured in an array.
An example of a typical 6T SRAM cell circuit is shown in FIG. 1. As shown in FIG. 1, the memory cell includes transistors M1, M2, M3, and M4 forming two inverters. In particular, PMOS transistors M1 and M3 serve as pull-up transistors and NMOS transistors M2 and M4 serve as pull-down transistors. Access to the memory cell is enabled by the word line WL, which controls the two access transistors M5 and M6. Transistors M5 and M6 control whether the memory cell should be connected to the bit lines BL and BLB. The SRAM cell of FIG. 1 has three states, standby (i.e., idle), read, and write.